1. Field of the Invention
The present invention relates to antifuses. More particularly, the present invention relates to antifuses suitable for improving the integration of a semiconductor device.
2. Background of the Related Art
Generally, an antifuse is the opposite of a fuse. The antifuse is formed in a default OFF-state, and is switched to an ON-state when a predetermined condition occurs. In its default OFF-state, the antifuse is an insulator with an electric resistance of several megaOhms (M.OMEGA.). In the ON-state, the electrical resistance of the antifuse drops to several hundred ohms.
The antifuse is switched from an OFF-state to an ON-state by applying a voltage of a predetermined level (7 to 10V) to first and second conductive layers. This causes a breakdown in the insulator interposed between the first and second conductive layers, thus switching the antifuse to an ON-state.
A field programmable gate array (FPGA) is a semi-custom logic integrated circuit (IC), which is less expensive and less time consuming to develop than standard Ics. Gates, i.e., basic logic devices, are arranged in parallel, and a logic integrated circuit (IC) is formed nonlinearly, thus making a user-desired circuit.
An antifuse for the FPGA is formed of amorphous silicon interposed between two conductors that are electrically separated from each other. Since the amorphous silicon has a high resistance value, it is an insulator. When an electric field is selectively created in one of the two conductors, as needed, the amorphous silicon is melted to connect the two conductors to each other, thus forming a gate array.
As shown in FIG. 1, the antifuse includes a first conductive layer 11 formed on a predetermined portion of a semiconductor substrate (not shown), an inter metal dielectric (IMD) layer 12 formed over the entire first conductive layer 11 and having a via hole whose upper portion is rounded, an amorphous silicon film 14 formed on an exposed portion of the first conductive layer 11 and a predetermined portion of the IMD layer 12, and a second conductive layer 16 formed on a predetermined portion of the amorphous silicon film 14.
FIGS. 2A-2C show a related art method of fabricating the antifuse shown in FIG. 1. The first conductive layer 11 is formed on a predetermined portion of the semiconductor substrate (not shown), and the IMD layer 12 is formed over the entire first conductive layer 11. A first photosensitive layer 13 is then applied to the IMD layer 12. The first photosensitive layer 13 is selectively exposed to light and developed so that it is removed over a region where the via hole will be formed. The IMD layer 12 is then selectively etched to form the via hole, using the first photosensitive layer 13 as a mask.
As shown in FIG. 2B, the first photosensitive layer 13 is removed, and the edges of the selectively etched IMD layer 12 are etched by an Ar sputtering technique so that the upper portion of the via hole is rounded. The amorphous silicon film 14 and the second photosensitive layer 15 are formed on the IMD layer 12, including the via hole. The second photosensitive layer 15 is then selectively exposed to light and developed so that it remains on a predetermined portion of the IMD layer 12 around the via hole. The amorphous silicon film 14 is then selectively etched, using the second photosensitive layer 15 as a mask.
Referring to FIG. 2C, after the second photosensitive layer 15 is removed, a second metal layer and a fourth photosensitive layer are formed on the IMD layer 12, including the selectively etched amorphous silicon film 14. After that, the fourth photosensitive layer is selectively exposed to light and developed so that it remains on a predetermined portion of the amorphous silicon film 14 around the via hole. The second metal layer is then selectively etched, using the fourth photosensitive layer, which was selectively exposed to light and developed, as a mask. This forms the second conductive layer 16. The third photosensitive layer is then removed. In this way, a single antifuse is made in the via hole.
The related art antifuse and the method of forming the same have the following problems.
First, there is a limit as to the number of antifuses that can be obtained per unit area to increase the chip size.
Second, once the antifuse in the via hole is used, it cannot serve as an antifuse again, thus deteriorating the efficiency of the FPGA.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.